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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 12:00:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-05 12:00:23 -0700 |
| commit | 903cd58acf7c490e0b75e34742966dc62e61028f (patch) | |
| tree | 24ed0acd4627da70e762abfb362a20fa3ae64b49 /techlibs/xilinx/Makefile.inc | |
| parent | 58ec1df4c26599338f2f45941ed8ca402abfe607 (diff) | |
| parent | aa1491add3722e4cfae35755cc4cecfd3e5a6c82 (diff) | |
| download | yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.gz yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.bz2 yosys-903cd58acf7c490e0b75e34742966dc62e61028f.zip | |
Merge pull request #1312 from YosysHQ/xaig_arrival
Allow arrival times of sequential outputs to be specified to abc9
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 2b1af289c..2efcf7d90 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -39,6 +39,9 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut)) |