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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-03 18:50:33 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-07 01:00:29 +0100 |
| commit | 95c46ccc555769cd9d24bae27e0b7264f06e3d66 (patch) | |
| tree | de5a3e2df77665914d1bd39c7eb01fabf40a480e /techlibs/xilinx/Makefile.inc | |
| parent | 1784d25f53abaf4b457e180af49dddca8718d88d (diff) | |
| download | yosys-95c46ccc555769cd9d24bae27e0b7264f06e3d66.tar.gz yosys-95c46ccc555769cd9d24bae27e0b7264f06e3d66.tar.bz2 yosys-95c46ccc555769cd9d24bae27e0b7264f06e3d66.zip | |
xilinx: Add support for Spartan 3A DSP block RAMs.
Part of #1550
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 3f2fbcc85..60b4ace1c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -27,6 +27,7 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt)) |