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author | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 18:11:46 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 18:11:46 -0700 |
commit | 2228cef62f8550f85b203752681e2abeef1197ea (patch) | |
tree | 77578bc790131eb6d7e6abc0a2a5f605e91de3c1 /techlibs/xilinx/abc.box | |
parent | 01f71085f281d4721386018c90d3f95b2864df5b (diff) | |
download | yosys-2228cef62f8550f85b203752681e2abeef1197ea.tar.gz yosys-2228cef62f8550f85b203752681e2abeef1197ea.tar.bz2 yosys-2228cef62f8550f85b203752681e2abeef1197ea.zip |
Add flops as blackboxes
Diffstat (limited to 'techlibs/xilinx/abc.box')
-rw-r--r-- | techlibs/xilinx/abc.box | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 6e9e1faf6..a4182ed63 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -40,3 +40,23 @@ RAM64X1D 4 0 15 2 RAM128X1D 5 0 17 2 - - - - - - - - 314 314 314 314 314 314 292 - - 347 347 347 347 347 347 296 - - - - - - - - - - + +# Inputs: C CE D R +# Outputs: Q +FDRE 6 0 4 1 +- - - - + +# Inputs: C CE D S +# Outputs: Q +FDSE 7 0 4 1 +- - - - + +# Inputs: C CE CLR D +# Outputs: Q +FDCE 8 0 4 1 +- - 404 - + +# Inputs: C CE D PRE +# Outputs: Q +FDPE 9 0 4 1 +- - - 404 |