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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-26 11:32:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-26 11:32:02 -0700 |
| commit | 4311b9b583488817aaae0019f6ebc47deb030644 (patch) | |
| tree | b8691b0814832da19fab6cd837a83936e2ef7e4c /techlibs/xilinx/abc.box | |
| parent | 3981eba999e1116f8f065451c6a71b8d3686b1bf (diff) | |
| download | yosys-4311b9b583488817aaae0019f6ebc47deb030644.tar.gz yosys-4311b9b583488817aaae0019f6ebc47deb030644.tar.bz2 yosys-4311b9b583488817aaae0019f6ebc47deb030644.zip | |
Blackboxes
Diffstat (limited to 'techlibs/xilinx/abc.box')
| -rw-r--r-- | techlibs/xilinx/abc.box | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 9653fe5b8..4d907c7e2 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -3,18 +3,18 @@ # F7BMUX slower than F7AMUX # Inputs: I0 I1 S0 # Outputs: O -F7BMUX 1 1 3 1 +F7BMUX 1 0 3 1 217 223 296 # Inputs: I0 I1 S0 # Outputs: O -MUXF8 2 1 3 1 +MUXF8 2 0 3 1 104 94 273 # CARRY4 + CARRY4_[ABCD]X # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 -CARRY4 3 1 10 8 +CARRY4 3 0 10 8 271 536 379 - - - 340 - - - 157 494 465 445 - - 433 469 - - 228 592 540 520 356 - 512 548 292 - @@ -27,13 +27,13 @@ CARRY4 3 1 10 8 # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Outputs: DPO SPO -RAM64X1D 4 1 15 2 +RAM64X1D 4 0 15 2 - - - - - - - 124 124 124 124 124 124 - - 124 124 124 124 124 124 - - - - - - 124 - - # SLICEM/A6LUT + F7[AB]MUX # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Outputs: DPO SPO -RAM128X1D 5 1 17 2 +RAM128X1D 5 0 17 2 - - - - - - - - 314 314 314 314 314 314 292 - - 347 347 347 347 347 347 296 - - - - - - - - - - |