diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 08:58:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 08:58:57 -0700 |
| commit | ae89e6ab26d2d87a604e20ebc14dcda8c9901585 (patch) | |
| tree | a8b9fb4f00eef4abaa1c476e488ded535f372dc6 /techlibs/xilinx/abc.box | |
| parent | 4f44e3399ba6c959c830943c44c4ad728be895fa (diff) | |
| download | yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.tar.gz yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.tar.bz2 yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.zip | |
Add whitebox support to DRAM
Diffstat (limited to 'techlibs/xilinx/abc.box')
| -rw-r--r-- | techlibs/xilinx/abc.box | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 57ea1670c..92ea5537b 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -25,3 +25,17 @@ CARRY4 3 1 10 8 - 469 548 528 - 205 558 618 - - 292 376 - - 226 330 - - - 380 - - - 227 + +# SLICEM/A6LUT +# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE +# Outputs: DPO SPO +RAM64X1D 4 1 15 2 +- - - - - - - 124 124 124 124 124 124 - - +124 124 124 124 124 124 - - - - - - 124 - - + +# SLICEM/A6LUT + F7[AB]MUX +# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE +# Outputs: DPO SPO +RAM128X1D 5 1 17 2 +- - - - - - - - 314 314 314 314 314 314 292 - - +347 347 347 347 347 347 296 - - - - - - - - - - |