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authorEddie Hung <eddie@fpgeh.com>2020-03-04 11:28:14 -0800
committerEddie Hung <eddie@fpgeh.com>2020-03-04 11:31:12 -0800
commit512596760b947a9ac9088856490970d0930dd951 (patch)
treefcb8e522a04181f0bfa04e27d64de75626c01a64 /techlibs/xilinx/abc9_map.v
parentf65fc845e53e12d01077604aa077c93fa3cac7f2 (diff)
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xilinx: cleanup DSP48E1 handling for abc9
Diffstat (limited to 'techlibs/xilinx/abc9_map.v')
-rw-r--r--techlibs/xilinx/abc9_map.v45
1 files changed, 11 insertions, 34 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 5d21bac07..81bcc8ac9 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -771,38 +771,15 @@ module DSP48E1 (
.RSTM(RSTM),
.RSTP(RSTP)
);
-
- generate
- wire [29:0] $A;
- wire [17:0] $B;
- wire [47:0] $C;
- wire [24:0] $D;
- wire [47:0] $PCIN;
-
- if (PREG == 0) begin
- if (MREG == 0 && AREG == 0) assign $A = A;
- else assign $A = 30'bx;
- if (MREG == 0 && BREG == 0) assign $B = B;
- else assign $B = 18'bx;
- if (MREG == 0 && DREG == 0) assign $D = D;
- else assign $D = 25'bx;
-
- if (CREG == 0) assign $C = C;
- else assign $C = 48'bx;
-
- assign $PCIN = PCIN;
- end
- else begin
- assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx, $PCIN = 48'bx;
- end
-
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")
- $__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
- else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")
- $__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
- else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")
- $__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
- else
- $error("Invalid DSP48E1 configuration");
- endgenerate
+ $__ABC9_DSP48E1 #(
+ .AREG(AREG),
+ .BREG(BREG),
+ .CREG(CREG),
+ .DREG(DREG),
+ .MREG(MREG),
+ .PREG(PREG),
+ .USE_DPORT(USE_DPORT),
+ .USE_MULT(USE_MULT)
+ ) dsp_comb (
+ .$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
endmodule