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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 11:13:50 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 11:13:50 -0800 |
| commit | 789211d9b3a6892c72d22a09bf2299075337f9f9 (patch) | |
| tree | 7568fab43428a152e64f326585bde668d664129d /techlibs/xilinx/abc9_map.v | |
| parent | 134e70e8e7798dd1e841b8deac2165c9f334ba09 (diff) | |
| download | yosys-789211d9b3a6892c72d22a09bf2299075337f9f9.tar.gz yosys-789211d9b3a6892c72d22a09bf2299075337f9f9.tar.bz2 yosys-789211d9b3a6892c72d22a09bf2299075337f9f9.zip | |
Fix incorrect $__ABC9_ASYNC[01] box
Diffstat (limited to 'techlibs/xilinx/abc9_map.v')
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 2cabe57d7..a3f9e311e 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -186,7 +186,7 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC1 below ); // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -204,7 +204,7 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC0 below ); // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end endgenerate $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); |