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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 18:59:40 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-05 18:59:40 +0100 |
| commit | 0671ae7d79ead3f7c109ed41ea7ad5e5767f418a (patch) | |
| tree | eff88fad0d90d4a6fd92c6ebda512d5bc010dc2b /techlibs/xilinx/abc9_model.v | |
| parent | 34d2fbd2f96a8789aa7eb655318308e11949eb7a (diff) | |
| parent | 21ce1b37fbc93562942c10f631c7f415f8fdba2e (diff) | |
| download | yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.tar.gz yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.tar.bz2 yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.zip | |
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 15d12c89f..782c53ab6 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -33,6 +33,11 @@ endmodule module \$__ABC9_FF_ (input D, output Q); endmodule +(* abc9_box_id = (9000+DELAY) *) +module \$__ABC9_DELAY (input I, output O); + parameter DELAY = 0; +endmodule + // Box to emulate async behaviour of FDC* (* abc9_box_id = 1000, lib_whitebox *) module \$__ABC9_ASYNC0 (input A, S, output Y); |