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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-22 14:22:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-23 19:02:27 -0800 |
| commit | 7858cf20a9fa3cec6993bcda39f84974d2793429 (patch) | |
| tree | f74c9de41fa80445f97396cc94ffc643a46b6ac8 /techlibs/xilinx/abc9_model.v | |
| parent | da6abc014987ef562a577dc374bcb03aad9256cd (diff) | |
| download | yosys-7858cf20a9fa3cec6993bcda39f84974d2793429.tar.gz yosys-7858cf20a9fa3cec6993bcda39f84974d2793429.tar.bz2 yosys-7858cf20a9fa3cec6993bcda39f84974d2793429.zip | |
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 204fa883f..15d12c89f 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -42,7 +42,7 @@ endmodule // Box to emulate async behaviour of FDP* (* abc9_box_id = 1001, lib_whitebox *) module \$__ABC9_ASYNC1 (input A, S, output Y); - assign Y = S ? 1'b0 : A; + assign Y = S ? 1'b1 : A; endmodule // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} |