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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
| commit | b6a1f627b5871e750fe6a559fbb42334c7de8b84 (patch) | |
| tree | f1b284aebe30d0f7eabd9e8919b4275a38ff2ae4 /techlibs/xilinx/abc9_model.v | |
| parent | 5aaa19f1ab33394accbe633cd96a3fbe281dd09a (diff) | |
| parent | 5ebdc0f8e07989b79337ced0553bd28819a8cf3e (diff) | |
| download | yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.gz yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.bz2 yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.zip | |
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 204fa883f..782c53ab6 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -33,6 +33,11 @@ endmodule module \$__ABC9_FF_ (input D, output Q); endmodule +(* abc9_box_id = (9000+DELAY) *) +module \$__ABC9_DELAY (input I, output O); + parameter DELAY = 0; +endmodule + // Box to emulate async behaviour of FDC* (* abc9_box_id = 1000, lib_whitebox *) module \$__ABC9_ASYNC0 (input A, S, output Y); @@ -42,7 +47,7 @@ endmodule // Box to emulate async behaviour of FDP* (* abc9_box_id = 1001, lib_whitebox *) module \$__ABC9_ASYNC1 (input A, S, output Y); - assign Y = S ? 1'b0 : A; + assign Y = S ? 1'b1 : A; endmodule // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} |