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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
| commit | 020606f81c39df234d7a3f5e3e605e5f27422d87 (patch) | |
| tree | 8334168ea6ad76983226fa3bbc631ff151d4fedd /techlibs/xilinx/abc9_unmap.v | |
| parent | 36d79c80d05f93cd4cb565fe7a92d7cb88683852 (diff) | |
| parent | b5f60e055d07579a2d4f23fc053ca030f103f377 (diff) | |
| download | yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.gz yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.bz2 yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.zip | |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index ad6469702..46526007d 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -20,6 +20,15 @@ // ============================================================================ +(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *) +module \$__ABC9_ASYNC01 (input A, S, output Y); + assign Y = A; +endmodule + +module \$__ABC9_FF_ (input D, output Q); + assign Q = D; +endmodule + module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); assign Y = A; endmodule |