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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-12 15:25:30 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 12d70ca8fbad73f2615e711e786f8b90fa005bee (patch) | |
| tree | 6459527e212b6e0ac65d99ad023606b6afd5e9f4 /techlibs/xilinx/abc9_unmap.v | |
| parent | 46a89d7264f597be9ad10390fa44c22e16538548 (diff) | |
| download | yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.tar.gz yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.tar.bz2 yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.zip | |
xilinx: improve specify functionality
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index f2342ce62..c02cc196a 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -29,10 +29,10 @@ module $__ABC9_FF_(input D, output Q); assign Q = D; endmodule -module $__ABC9_LUT6(input A, input [5:0] S, output Y); +module $__ABC9_RAM6(input A, input [5:0] S, output Y); assign Y = A; endmodule -module $__ABC9_LUT7(input A, input [6:0] S, output Y); +module $__ABC9_RAM7(input A, input [6:0] S, output Y); assign Y = A; endmodule |