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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 11:28:14 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 11:31:12 -0800 |
| commit | 512596760b947a9ac9088856490970d0930dd951 (patch) | |
| tree | fcb8e522a04181f0bfa04e27d64de75626c01a64 /techlibs/xilinx/abc9_unmap.v | |
| parent | f65fc845e53e12d01077604aa077c93fa3cac7f2 (diff) | |
| download | yosys-512596760b947a9ac9088856490970d0930dd951.tar.gz yosys-512596760b947a9ac9088856490970d0930dd951.tar.bz2 yosys-512596760b947a9ac9088856490970d0930dd951.zip | |
xilinx: cleanup DSP48E1 handling for abc9
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index c02cc196a..b8d0c4dc0 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -36,8 +36,7 @@ module $__ABC9_RAM7(input A, input [6:0] S, output Y); assign Y = A; endmodule -(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *) -module $ABC9_DSP48E1( +module $__ABC9_DSP48E1( input [29:0] $A, input [17:0] $B, input [47:0] $C, @@ -48,5 +47,14 @@ module $ABC9_DSP48E1( output [47:0] P, output [47:0] PCOUT ); + parameter integer AREG = 1; + parameter integer BREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer PREG = 1; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + assign P = $P, PCOUT = $PCOUT; endmodule |