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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:50:07 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-06 16:50:07 -0800 |
| commit | ce765aa4def09bd8b0161425ee40ee55f62e33ff (patch) | |
| tree | 2a91632d31dab23188d6cb1b4bef16b47518cbe4 /techlibs/xilinx/abc9_unmap.v | |
| parent | 66698cb6fd0e33a27197b7412e094dc77363b5e5 (diff) | |
| parent | 98ee8c14df763973d47c8c952d462eb9407f6787 (diff) | |
| download | yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.tar.gz yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.tar.bz2 yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.zip | |
Merge pull request #1181 from YosysHQ/xaig_dff
"abc9 -dff" option for sequential synthesis
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index 64135e9a7..f2342ce62 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -20,6 +20,15 @@ // ============================================================================ +(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *) +module $__ABC9_ASYNC01(input A, S, output Y); + assign Y = A; +endmodule + +module $__ABC9_FF_(input D, output Q); + assign Q = D; +endmodule + module $__ABC9_LUT6(input A, input [5:0] S, output Y); assign Y = A; endmodule |