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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 22:55:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 22:55:18 -0700 |
| commit | 3879ca13983a6e3f7d4653b1d80dacd14fbe82df (patch) | |
| tree | 52fd4ecb68e7df0e0afbcb8c8333e960cc380d23 /techlibs/xilinx/abc9_xc7.box | |
| parent | 3c6e5d82a62650a48027d35e6d92a7a88ad43a16 (diff) | |
| download | yosys-3879ca13983a6e3f7d4653b1d80dacd14fbe82df.tar.gz yosys-3879ca13983a6e3f7d4653b1d80dacd14fbe82df.tar.bz2 yosys-3879ca13983a6e3f7d4653b1d80dacd14fbe82df.zip | |
Do not require changes to cells_sim.v; try and work out comb model
Diffstat (limited to 'techlibs/xilinx/abc9_xc7.box')
| -rw-r--r-- | techlibs/xilinx/abc9_xc7.box | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 6814b101f..24b1898a4 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -44,7 +44,7 @@ CARRY4 4 1 10 8 # Box to emulate async behaviour of FD[CP]* # Inputs: A S # Outputs: Y -$__ABC_ASYNC 1000 0 2 1 +$__ABC9_ASYNC 1000 0 2 1 0 764 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to |