Merge branch 'master' of github.com:YosysHQ/yosys

1 files changed, 126 insertions, 48 deletions

diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 9fb1cc0ef..64170546c 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -1,64 +1,142 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 #                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
 
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+#     as their corresponding module definition
+#     (with exceptions detailed below)
 
-# Average across F7[AB]MUX
-# Inputs: I0 I1 S0
-# Outputs: O
-MUXF7 1 1 3 1
-204 208 286
+# Box 1 : MUXF7
+#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453
+# name ID w/b ins outs
+MUXF7  1  1   3   1
+#I0 I1  S0
+204 208 286 # O
 
-# Inputs: I0 I1 S0
-# Outputs: O
-MUXF8 2 1 3 1
-104 94 273
+# Box 2 : MUXF8
+#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464
+# name ID w/b ins outs
+MUXF8  2  1   3   1
+#I0 I1 S0
+104 94 273 # O
 
-# Box containing MUXF7.[AB] + MUXF8,
-#   Necessary to make these an atomic unit so that
-#   ABC cannot optimise just one of the MUXF7 away
-#   and expect to save on its delay
-# Inputs: I0 I1 I2 I3 S0 S1
-# Outputs: O
-$__MUXF78 3 1 6 1
-294 297 311 317 390 273
+# Box 3 : $__MUXF78
+#         (private cell used to preserve 2xMUXF7 + 1xMUXF8
+#          an atomic unit so that ABC cannot optimise just
+#          one of the MUXF7 away and expect to save on its
+#          delay, since MUXF8 is only reachable through an
+#          MUXF7)
+# name    ID w/b ins outs
+$__MUXF78 3  1   6   1
+#I0 I1  I2  I3  S0  S1
+294 297 311 317 390 273 # O
 
-# CARRY4 + CARRY4_[ABCD]X
-# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
-# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
-#   (NB: carry chain input/output must be last
-#        input/output and the entire bus has been
+# Box 4 : CARRY4 + CARRY4_[ABCD]X
+#   (Exception: carry chain input/output must be the
+#        last input and output and the entire bus has been
 #        moved there overriding the otherwise
 #        alphabetical ordering)
-CARRY4 4 1 10 8
-482 -   -   -   -   223 -   -   -   222
-598 407 -   -   -   400 205 -   -   334
-584 556 537 -   -   523 558 226 -   239
-642 615 596 438 -   582 618 330 227 313
-536 379 -   -   -   340 -   -   -   271
-494 465 445 -   -   433 469 -   -   157
-592 540 520 356 -   512 548 292 -   228
-580 526 507 398 385 508 528 378 380 114
+#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46
+# name ID w/b ins outs
+CARRY4 4  1   10  8
+#CYINIT DI0 DI1 DI2 DI3 S0  S1  S2  S3  CI
+482     -   -   -   -   223 -   -   -   222 # O0
+598     407 -   -   -   400 205 -   -   334 # O1
+584     556 537 -   -   523 558 226 -   239 # O2
+642     615 596 438 -   582 618 330 227 313 # O3
+536     379 -   -   -   340 -   -   -   271 # CO0
+494     465 445 -   -   433 469 -   -   157 # CO1
+592     540 520 356 -   512 548 292 -   228 # CO2
+580     526 507 398 385 508 528 378 380 114 # CO3
 
+# Box 1000 : $__ABC9_ASYNC0
+#            (private cell to emulate async behaviour of FDC*)
+# name         ID   w/b ins outs
+$__ABC9_ASYNC0 1000 1   2   1
+#A S
+0  764 # Y
+
+# Box 1001 : $__ABC9_ASYNC1
+#            (private cell to emulate async behaviour of FDP*)
+# name         ID   w/b ins outs
+$__ABC9_ASYNC1 1001 1   2   1
+#A S
+0  764 # Y
+
+# Flop boxes:
+# * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+#                   https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+# * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality
+
+# Box 1100 : FDRE
+# name ID   w/b ins outs
+FDRE   1100 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1101 : FDRE_1
+# name ID   w/b ins outs
+FDRE_1 1101 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1102 : FDSE
+# name ID   w/b ins outs
+FDSE   1102 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1103 : FDSE_1
+# name ID   w/b ins outs
+FDSE_1 1103 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1104 : FDCE
+# name ID   w/b ins outs
+FDCE   1104 1   5   1
+#C CE  CLR D   $abc9_currQ
+#0 109 764 -46 0
+0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1105 : FDCE_1
+# name ID   w/b ins outs
+FDCE_1 1105 1   5   1
+#C CE  CLR D   $abc9_currQ
+#0 109 764 -46 0
+0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1106 : FDPE
+# name ID   w/b ins outs
+FDPE   1106 1   5   1
+#C CE  D   PRE $abc9_currQ
+#0 109 -46 764 0
+0 109 0   764 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1107 : FDPE_1
+# name ID   w/b ins outs
+FDPE_1 1107 1   5   1
+#C CE  D   PRE $abc9_currQ
+#0 109 -46 764 0
+0 109 0   764 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 2000 : $__ABC9_LUT6
+#            (private cell to emulate async behaviour of LUTRAMs)
 # SLICEM/A6LUT
-# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
-#   Necessary since RAMD* and SRL* have both combinatorial (i.e.
-#   same-cycle read operation) and sequential (write operation
-#   is only committed on the next clock edge).
-#   To model the combinatorial path, such cells have to be split
-#   into comb and seq parts, with this box modelling only the former.
-# Inputs: A S0 S1 S2 S3 S4 S5
-# Outputs: Y
-$__ABC9_LUT6 2000 0 7 1
-0 642 631 472 407 238 127
+# name       ID   w/b ins outs
+$__ABC9_LUT6 2000 0   7   1
+#A S0  S1  S2  S3  S4  S5
+0  642 631 472 407 238 127 # Y
 
-# SLICEM/A6LUT + F7BMUX
-# Box to emulate comb/seq behaviour of RAMD128
-# Inputs: A S0 S1 S2 S3 S4 S5 S6
-# Outputs: DPO SPO
+# Box 2001 : $__ABC9_LUT6
+#            (private cell to emulate async behaviour of LUITRAMs)
+# name       ID   w/b ins outs
 $__ABC9_LUT7 2001 0 8 1
-0 1047 1036 877 812 643 532 478
+#A S0   S1   S2  S3  S4  S5  S6
+0  1047 1036 877 812 643 532 478 # Y
 
 # Boxes used to represent the comb behaviour of various modes
 #   of DSP48E1