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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 10:53:38 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-08 10:53:38 -0700 |
| commit | 9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f (patch) | |
| tree | 526027efe405ddd8741558d150a341478d269d1f /techlibs/xilinx/abc9_xc7_nowide.lut | |
| parent | 472b5d33a624c2e414ce733c1cda0b97bce24094 (diff) | |
| parent | a5ac33f230b5dd20273f6636e5b573ef0478b8f9 (diff) | |
| download | yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.tar.gz yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.tar.bz2 yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.zip | |
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Rename abc_* names/attributes to more precisely be abc9_*
Diffstat (limited to 'techlibs/xilinx/abc9_xc7_nowide.lut')
| -rw-r--r-- | techlibs/xilinx/abc9_xc7_nowide.lut | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_xc7_nowide.lut b/techlibs/xilinx/abc9_xc7_nowide.lut new file mode 100644 index 000000000..fab48c879 --- /dev/null +++ b/techlibs/xilinx/abc9_xc7_nowide.lut @@ -0,0 +1,10 @@ +# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf +# and https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json + +# K area delay +1 1 127 +2 2 127 238 +3 3 127 238 407 +4 3 127 238 407 472 +5 3 127 238 407 472 631 +6 5 127 238 407 472 631 642 |