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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:52:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:52:27 -0700 |
| commit | 54284aaa986800b8623d401fd93cf92d25d13713 (patch) | |
| tree | 3d2d52add727a3388533e89ec2b178ee4adf17d1 /techlibs/xilinx/abc_map.v | |
| parent | 96f00e9147967b587ee3b0118b944464b06da0b6 (diff) | |
| download | yosys-54284aaa986800b8623d401fd93cf92d25d13713.tar.gz yosys-54284aaa986800b8623d401fd93cf92d25d13713.tar.bz2 yosys-54284aaa986800b8623d401fd93cf92d25d13713.zip | |
Remove delays from abc_map.v
Diffstat (limited to 'techlibs/xilinx/abc_map.v')
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index dc5032d23..1d8604ddb 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -20,8 +20,6 @@ // ============================================================================ -// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 - module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -205,9 +203,8 @@ module SRL16E ( endmodule module SRLC32E ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output Q, - (* abc_arrival=1114 *) output Q31, + output Q, + output Q31, input [4:0] A, input CE, CLK, D ); |