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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 10:51:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 10:51:39 -0700 |
| commit | 9314a0a42ec05e82d2d3d77aebddfb06271a4730 (patch) | |
| tree | 9251ba658029484731a53e68bd8e14d2c5f8a3e8 /techlibs/xilinx/abc_map.v | |
| parent | 13424352cc8dca5f08ad22aa42066dc7f62afea5 (diff) | |
| download | yosys-9314a0a42ec05e82d2d3d77aebddfb06271a4730.tar.gz yosys-9314a0a42ec05e82d2d3d77aebddfb06271a4730.tar.bz2 yosys-9314a0a42ec05e82d2d3d77aebddfb06271a4730.zip | |
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
Diffstat (limited to 'techlibs/xilinx/abc_map.v')
0 files changed, 0 insertions, 0 deletions