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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:14:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:14:40 -0700 |
| commit | bbab6086918f8af3a8a09c2be56208fc29ef7068 (patch) | |
| tree | 378ddd9860014548bee29a57d5eb285fa75b244d /techlibs/xilinx/abc_map.v | |
| parent | fad15d276dd9746b41a2d3e1592285ad4362fe21 (diff) | |
| download | yosys-bbab6086918f8af3a8a09c2be56208fc29ef7068.tar.gz yosys-bbab6086918f8af3a8a09c2be56208fc29ef7068.tar.bz2 yosys-bbab6086918f8af3a8a09c2be56208fc29ef7068.zip | |
Remove SRL* delays from cells_sim.v
Diffstat (limited to 'techlibs/xilinx/abc_map.v')
0 files changed, 0 insertions, 0 deletions