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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 19:37:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 19:37:45 -0700 |
| commit | 1602516a8b2ebd432528e9ba39a00db4e6edc081 (patch) | |
| tree | 95ba21ae51fec3c369cd9aaf5efbc9adc7b361f7 /techlibs/xilinx/abc_unmap.v | |
| parent | e09f80479e6d16cf95c26e406bf06d81b94231f4 (diff) | |
| download | yosys-1602516a8b2ebd432528e9ba39a00db4e6edc081.tar.gz yosys-1602516a8b2ebd432528e9ba39a00db4e6edc081.tar.bz2 yosys-1602516a8b2ebd432528e9ba39a00db4e6edc081.zip | |
$__ABC_REG to have WIDTH parameter
Diffstat (limited to 'techlibs/xilinx/abc_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc_unmap.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 137829d65..ab007dfd2 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -27,7 +27,8 @@ module \$__ABC_LUT7 (input A, input [6:0] S, output Y); assign Y = A; endmodule -module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); +module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q); + parameter WIDTH = 1; assign O = I; endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) |