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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 18:33:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 18:33:29 -0700 |
| commit | 41256f48a5f3231e231cbdf9380a26128f272044 (patch) | |
| tree | c5e85310581d5087f4b83e1f5d730f66bad75a65 /techlibs/xilinx/abc_unmap.v | |
| parent | c83a66755553f47f40c591110e6bdcd722360d6c (diff) | |
| download | yosys-41256f48a5f3231e231cbdf9380a26128f272044.tar.gz yosys-41256f48a5f3231e231cbdf9380a26128f272044.tar.bz2 yosys-41256f48a5f3231e231cbdf9380a26128f272044.zip | |
Different approach to timing
Diffstat (limited to 'techlibs/xilinx/abc_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc_unmap.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 010041b73..8700393ab 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -27,10 +27,10 @@ module \$__ABC_LUT7 (input A, input [6:0] S, output Y); assign Y = A; endmodule -module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); +(* techmap_celltype = "$__ABC_DSP48E1_MULT_AREG $__ABC_DSP48E1_MULT_BREG $__ABC_DSP48E1_MULT_CREG $__ABC_DSP48E1_MULT_MREG $__ABC_DSP48E1_MULT_PREG $__ABC_DSP48E1_MULT_DPORT_AREG $__ABC_DSP48E1_MULT_DPORT_BREG $__ABC_DSP48E1_MULT_DPORT_CREG $__ABC_DSP48E1_MULT_DPORT_DREG $__ABC_DSP48E1_MULT_DPORT_ADREG $__ABC_DSP48E1_MULT_DPORT_MREG $__ABC_DSP48E1_MULT_DPORT_PREG " *) +module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output P, PCOUT); assign O = I; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) module \$__ABC_DSP48E1_MUX ( input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, |