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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
| commit | 052060f10906ca859d2313b86800e110bd34b79f (patch) | |
| tree | 356107e4270feb84046b984a98e0874f1436b2d9 /techlibs/xilinx/abc_xc7.box | |
| parent | 35fd9b04731d3bc944e1471b96668ef0cf7b51f1 (diff) | |
| parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
| download | yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.gz yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.bz2 yosys-052060f10906ca859d2313b86800e110bd34b79f.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/abc_xc7.box')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 633e2d484..69ff9aeab 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -3,17 +3,22 @@ # NB: Inputs/Outputs must be ordered alphabetically # (with exceptions for carry in/out) -# F7BMUX slower than F7AMUX +# Average across F7[AB]MUX # Inputs: I0 I1 S0 # Outputs: O -F7BMUX 1 1 3 1 -217 223 296 +F7MUX 1 1 3 1 +204 208 286 # Inputs: I0 I1 S0 # Outputs: O MUXF8 2 1 3 1 104 94 273 +# Inputs: I0 I1 I2 I3 S0 S1 +# Outputs: O +$__MUXF78 3 1 6 1 +294 297 311 317 390 273 + # CARRY4 + CARRY4_[ABCD]X # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 @@ -21,7 +26,7 @@ MUXF8 2 1 3 1 # input/output and the entire bus has been # moved there overriding the otherwise # alphabetical ordering) -CARRY4 3 1 10 8 +CARRY4 4 1 10 8 482 - - - - 223 - - - 222 598 407 - - - 400 205 - - 334 584 556 537 - - 523 558 226 - 239 @@ -34,21 +39,21 @@ CARRY4 3 1 10 8 # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE # Outputs: DPO SPO -RAM32X1D 4 0 13 2 +RAM32X1D 5 0 13 2 - - - - - - 631 472 407 238 127 - - 631 472 407 238 127 - - - - - - - - # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Outputs: DPO SPO -RAM64X1D 5 0 15 2 +RAM64X1D 6 0 15 2 - - - - - - - 642 631 472 407 238 127 - - 642 631 472 407 238 127 - - - - - - - - - # SLICEM/A6LUT + F7[AB]MUX # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Outputs: DPO SPO -RAM128X1D 6 0 17 2 +RAM128X1D 7 0 17 2 - - - - - - - - 1009 998 839 774 605 494 450 - - 1047 1036 877 812 643 532 478 - - - - - - - - - - |