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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:47:11 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:47:11 -0700 |
commit | c26c5563845d81048dea35c4aef5f4678e177b23 (patch) | |
tree | 966210f9e81cad2fd9180a9123e073bd55a17521 /techlibs/xilinx/abc_xc7.box | |
parent | 6b1b03d9f771addbd54358299faad181b589c9f8 (diff) | |
download | yosys-c26c5563845d81048dea35c4aef5f4678e177b23.tar.gz yosys-c26c5563845d81048dea35c4aef5f4678e177b23.tar.bz2 yosys-c26c5563845d81048dea35c4aef5f4678e177b23.zip |
xilinx to use abc_map.v with -max_iter 1
Diffstat (limited to 'techlibs/xilinx/abc_xc7.box')
-rw-r--r-- | techlibs/xilinx/abc_xc7.box | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 61b89b8af..554cc0cf0 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -42,12 +42,12 @@ CARRY4 4 1 10 8 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} # Inputs: A S0 S1 S2 S3 S4 S5 # Outputs: Y -$__ABC_LUTRAM6 2000 0 7 1 +$__ABC_LUT6 2000 0 7 1 0 642 631 472 407 238 127 # SLICEM/A6LUT + F7BMUX # Box to emulate comb/seq behaviour of RAMD128 # Inputs: A S0 S1 S2 S3 S4 S5 S6 # Outputs: DPO SPO -$__ABC_LUTRAM7 2001 0 8 1 +$__ABC_LUT7 2001 0 8 1 0 1047 1036 877 812 643 532 478 |