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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 10:23:29 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 10:23:29 -0700 |
commit | 988e6163abae4ed0a01952c221d17f70bed9c244 (patch) | |
tree | 02059005ba9d63fcdf95299b099123c7403f5360 /techlibs/xilinx/abc_xc7_nowide.lut | |
parent | 741ebba70a4036e71adcdad223ce111c4a025365 (diff) | |
download | yosys-988e6163abae4ed0a01952c221d17f70bed9c244.tar.gz yosys-988e6163abae4ed0a01952c221d17f70bed9c244.tar.bz2 yosys-988e6163abae4ed0a01952c221d17f70bed9c244.zip |
Add _nowide variants of LUT libraries in -nowidelut flows
Diffstat (limited to 'techlibs/xilinx/abc_xc7_nowide.lut')
-rw-r--r-- | techlibs/xilinx/abc_xc7_nowide.lut | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc_xc7_nowide.lut b/techlibs/xilinx/abc_xc7_nowide.lut new file mode 100644 index 000000000..fab48c879 --- /dev/null +++ b/techlibs/xilinx/abc_xc7_nowide.lut @@ -0,0 +1,10 @@ +# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf +# and https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json + +# K area delay +1 1 127 +2 2 127 238 +3 3 127 238 407 +4 3 127 238 407 472 +5 3 127 238 407 472 631 +6 5 127 238 407 472 631 642 |