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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-07-20 22:09:44 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-07-20 22:09:44 +0000 |
| commit | 42fb75c57092714fce0394817154cdd5d63e9d2b (patch) | |
| tree | a607d91aff5aeaea54c51fa813f75a3030a3fee8 /techlibs/xilinx/arith_map.v | |
| parent | 654864658f17a26d760995462e57481ff81b037c (diff) | |
| download | yosys-42fb75c57092714fce0394817154cdd5d63e9d2b.tar.gz yosys-42fb75c57092714fce0394817154cdd5d63e9d2b.tar.bz2 yosys-42fb75c57092714fce0394817154cdd5d63e9d2b.zip | |
smtio: Emit `mode: start` options before `set-logic` command and any other options after it.
Refer to the SMT-LIB specification, section 4.1.7. According to the spec, some options can only be specified in `start` mode. Once the solver sees `set-logic`, it moves to `assert` mode.
Diffstat (limited to 'techlibs/xilinx/arith_map.v')
0 files changed, 0 insertions, 0 deletions