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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-19 00:17:02 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-19 00:17:02 +0200 |
| commit | 85a1bb17edca9ab105ae5e11aaa65b5a85c8fe86 (patch) | |
| tree | 60ed1014fa5395aa1c6c9e02deca231cb2291cc2 /techlibs/xilinx/arith_map.v | |
| parent | eed05953f820439178b2138cef7d53d50528354a (diff) | |
| download | yosys-85a1bb17edca9ab105ae5e11aaa65b5a85c8fe86.tar.gz yosys-85a1bb17edca9ab105ae5e11aaa65b5a85c8fe86.tar.bz2 yosys-85a1bb17edca9ab105ae5e11aaa65b5a85c8fe86.zip | |
satgen: Move importCell out of the header.
This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
Diffstat (limited to 'techlibs/xilinx/arith_map.v')
0 files changed, 0 insertions, 0 deletions