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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:45 -0700 |
| commit | ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c (patch) | |
| tree | 15c24a82884ffd0fabdd24ddfc48e2c16b08d583 /techlibs/xilinx/arith_map.v | |
| parent | 0f094fba08b69baa2329e749daf19f41a624a0a0 (diff) | |
| download | yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.tar.gz yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.tar.bz2 yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.zip | |
Instead of MUXCY/XORCY use CARRY4 (with timing)
Diffstat (limited to 'techlibs/xilinx/arith_map.v')
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 09a5f07e8..5c848d4e6 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -180,7 +180,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part + CARRY4 carry4_1st_part ( .CYINIT(CI), .CI (1'd0), @@ -207,7 +207,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full + CARRY4 carry4_1st_full ( .CYINIT(CI), .CI (1'd0), |