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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 23:21:52 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 23:21:52 +0100 |
| commit | ec2eef89fab03beb655f4fe3a16b002d3bf439f7 (patch) | |
| tree | 3980298c8c40b8bab28a0a67399360c56b6179ee /techlibs/xilinx/brams.v | |
| parent | 7cc5192125244d3fd990f3043d619262066ff962 (diff) | |
| download | yosys-ec2eef89fab03beb655f4fe3a16b002d3bf439f7.tar.gz yosys-ec2eef89fab03beb655f4fe3a16b002d3bf439f7.tar.bz2 yosys-ec2eef89fab03beb655f4fe3a16b002d3bf439f7.zip | |
Towards Xilinx bram support
Diffstat (limited to 'techlibs/xilinx/brams.v')
| -rw-r--r-- | techlibs/xilinx/brams.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v index a0baeaf04..a2724fe37 100644 --- a/techlibs/xilinx/brams.v +++ b/techlibs/xilinx/brams.v @@ -167,10 +167,10 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN input CLK2; input CLK3; - input [8:0] A1ADDR; + input [9:0] A1ADDR; output [17:0] A1DATA; - input [8:0] B1ADDR; + input [9:0] B1ADDR; input [17:0] B1DATA; input [1:0] B1EN; |