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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 17:15:56 -0700 |
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| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-15 09:18:27 -0700 |
| commit | 3a404be62a7b7fcc435857e20aa6c528f373b81c (patch) | |
| tree | 34157f9c4aea862a823e86a334784b465c7128ff /techlibs/xilinx/brams_init.py | |
| parent | e5109847c9a6c4b34a2d78442758773adfea2f4f (diff) | |
| download | yosys-3a404be62a7b7fcc435857e20aa6c528f373b81c.tar.gz yosys-3a404be62a7b7fcc435857e20aa6c528f373b81c.tar.bz2 yosys-3a404be62a7b7fcc435857e20aa6c528f373b81c.zip | |
Updated PGEN model to have level triggered reset (matches actual hardware behavior
Diffstat (limited to 'techlibs/xilinx/brams_init.py')
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