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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
| commit | 924d9d6e86a5e9a2294479345daac1c03d78008a (patch) | |
| tree | 04d28a2068b32c44c0aca2b8b815f6fc51cec427 /techlibs/xilinx/brams_map.v | |
| parent | ec92c8965960fa814c3663e987bc2a7eb80965e5 (diff) | |
| download | yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.tar.gz yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.tar.bz2 yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.zip | |
Added read-enable to memory model
Diffstat (limited to 'techlibs/xilinx/brams_map.v')
| -rw-r--r-- | techlibs/xilinx/brams_map.v | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v index cbfd4e1eb..7ea49158d 100644 --- a/techlibs/xilinx/brams_map.v +++ b/techlibs/xilinx/brams_map.v @@ -1,4 +1,4 @@ -module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [36863:0] INIT = 36864'bx; @@ -8,6 +8,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [8:0] A1ADDR; output [71:0] A1DATA; + input A1EN; input [8:0] B1ADDR; input [71:0] B1DATA; @@ -47,7 +48,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), - .ENARDEN(|1), + .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), @@ -65,7 +66,7 @@ endmodule // ------------------------------------------------------------------------ -module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [18431:0] INIT = 18432'bx; @@ -75,6 +76,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [8:0] A1ADDR; output [35:0] A1DATA; + input A1EN; input [8:0] B1ADDR; input [35:0] B1DATA; @@ -111,7 +113,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), - .ENARDEN(|1), + .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), @@ -129,7 +131,7 @@ endmodule // ------------------------------------------------------------------------ -module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 36; parameter CFG_ENABLE_B = 4; @@ -143,6 +145,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; + input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; @@ -181,7 +184,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOPADOP(DOP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), - .ENARDEN(|1), + .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), @@ -219,7 +222,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOPADOP(DOP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), - .ENARDEN(|1), + .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), @@ -242,7 +245,7 @@ endmodule // ------------------------------------------------------------------------ -module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 18; parameter CFG_ENABLE_B = 2; @@ -256,6 +259,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; + input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; @@ -294,7 +298,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOPADOP(DOP), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), - .ENARDEN(|1), + .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), @@ -332,7 +336,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOPADOP(DOP), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), - .ENARDEN(|1), + .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), |