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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 14:53:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 14:53:28 -0700 |
| commit | cbb85e40e87fbfb1602bb934ed76a97efb9e55c6 (patch) | |
| tree | 1afb529ee49da73f907916f8e0b1623d928102eb /techlibs/xilinx/cells_box.v | |
| parent | ece5c3ab38023abc251828b9379ea4eca9573abc (diff) | |
| download | yosys-cbb85e40e87fbfb1602bb934ed76a97efb9e55c6.tar.gz yosys-cbb85e40e87fbfb1602bb934ed76a97efb9e55c6.tar.bz2 yosys-cbb85e40e87fbfb1602bb934ed76a97efb9e55c6.zip | |
Add MUXCY and XORCY to cells_box.v
Diffstat (limited to 'techlibs/xilinx/cells_box.v')
| -rw-r--r-- | techlibs/xilinx/cells_box.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v index 7805e6306..ef6f81d27 100644 --- a/techlibs/xilinx/cells_box.v +++ b/techlibs/xilinx/cells_box.v @@ -8,3 +8,12 @@ module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule +(* abc_box_id = 3 *) +module MUXCY(output O, input CI, DI, S); + assign O = S ? CI : DI; +endmodule + +(* abc_box_id = 4 *) +module XORCY(output O, input CI, LI); + assign O = CI ^ LI; +endmodule |