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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-15 23:01:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-15 23:01:40 -0700 |
| commit | 29a8d4745eb4ecd2947694d02f51c9333bf3ac21 (patch) | |
| tree | dd48a298f27bac04a189e8cf6acb261b845724c0 /techlibs/xilinx/cells_map.v | |
| parent | 06f8f2654abdef8684bfe4f373ac42cb8c62ee2a (diff) | |
| download | yosys-29a8d4745eb4ecd2947694d02f51c9333bf3ac21.tar.gz yosys-29a8d4745eb4ecd2947694d02f51c9333bf3ac21.tar.bz2 yosys-29a8d4745eb4ecd2947694d02f51c9333bf3ac21.zip | |
Cleanup synth_xilinx
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index e7fb269e9..a35b0742b 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -95,7 +95,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q); MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6])); end end - else if (DEPTH < 129 || (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_)) begin + else if (DEPTH <= 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin // Handle cases where depth is just 1 over a convenient value, if (&_TECHMAP_CONSTMSK_L_) begin // For constant length, use the flop |