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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
| commit | 69fb3b8db21c8a50fa333bff3ef844af42729e0d (patch) | |
| tree | 1a62aebe9ece22b19b4087f2c5cb5581b571c270 /techlibs/xilinx/cells_map.v | |
| parent | 72323e11a4ee222c0ce928669d33333c46fb25aa (diff) | |
| parent | fa989e59e5a37d804d8a82050e022b8f4b7070d8 (diff) | |
| download | yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.gz yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.bz2 yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index b8e5bafc7..a15884ec4 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -331,7 +331,6 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y) endmodule `endif -`ifndef _ABC module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); output O; input I0, I1, I2, I3, S0, S1; @@ -364,4 +363,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); else MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule -`endif |