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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 12:00:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-05 12:00:23 -0700 |
| commit | 903cd58acf7c490e0b75e34742966dc62e61028f (patch) | |
| tree | 24ed0acd4627da70e762abfb362a20fa3ae64b49 /techlibs/xilinx/cells_map.v | |
| parent | 58ec1df4c26599338f2f45941ed8ca402abfe607 (diff) | |
| parent | aa1491add3722e4cfae35755cc4cecfd3e5a6c82 (diff) | |
| download | yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.gz yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.bz2 yosys-903cd58acf7c490e0b75e34742966dc62e61028f.zip | |
Merge pull request #1312 from YosysHQ/xaig_arrival
Allow arrival times of sequential outputs to be specified to abc9
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index b8e5bafc7..a15884ec4 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -331,7 +331,6 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y) endmodule `endif -`ifndef _ABC module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); output O; input I0, I1, I2, I3, S0, S1; @@ -364,4 +363,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); else MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule -`endif |