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| author | David Shah <dave@ds0.me> | 2019-07-16 16:46:41 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-16 16:47:53 +0100 |
| commit | 95c8d27b0bfdea330a62a18825dea3691b4affe2 (patch) | |
| tree | 930265835858e9f5068b0c50766b6f6e4d855237 /techlibs/xilinx/cells_map.v | |
| parent | 8da4c1ad8262216c5204c735f5297da33fed01fa (diff) | |
| download | yosys-95c8d27b0bfdea330a62a18825dea3691b4affe2.tar.gz yosys-95c8d27b0bfdea330a62a18825dea3691b4affe2.tar.bz2 yosys-95c8d27b0bfdea330a62a18825dea3691b4affe2.zip | |
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 6ebca0d54..8302e0b3a 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -366,7 +366,7 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); endmodule `endif -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); +module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] OUT); wire [47:0] P_48; DSP48E1 #( // Disable all registers @@ -388,8 +388,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({5'b0, A}), - .B(B), + .A({6'b0, A}), + .B({1'b0, B}), .C(48'b0), .D(24'b0), .P(P_48), |