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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 10:49:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 10:49:26 -0700 |
| commit | a02d1720a766ae1b993a9884e840f37b3d785b8f (patch) | |
| tree | d11cde6c9cb30afc8a54d49834d79facf94bb5a7 /techlibs/xilinx/cells_map.v | |
| parent | c5e31ac9c3c49f38ddcb6e613ef4a092d69f71a2 (diff) | |
| parent | eb663c75794d1249247ba88bf0bee835c98a8a85 (diff) | |
| download | yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.tar.gz yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.tar.bz2 yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 2eb9fa2c1..b8e5bafc7 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -24,9 +24,9 @@ module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLA (* techmap_celltype = "$_DFF_PN0_" *) module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule (* techmap_celltype = "$_DFF_NN1_" *) -module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule (* techmap_celltype = "$_DFF_PN1_" *) -module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; |