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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:46:18 -0700 |
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| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:46:18 -0700 |
| commit | 0364a5d811f79364f35b72935fe90bc188229c19 (patch) | |
| tree | 221646765409f5eddcd066dc72b4bb17097fd008 /techlibs/xilinx/cells_sim.v | |
| parent | 544843da717734ab9bd9bd88f71db2475fc3abc0 (diff) | |
| parent | 97587015748eb9f7e0d55a1121f604b8b462b45a (diff) | |
| download | yosys-0364a5d811f79364f35b72935fe90bc188229c19.tar.gz yosys-0364a5d811f79364f35b72935fe90bc188229c19.tar.bz2 yosys-0364a5d811f79364f35b72935fe90bc188229c19.zip | |
Merge branch 'eddie/fix_retime' into xc7srl
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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