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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:22:46 -0800 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:22:46 -0800 |
| commit | 21ce1b37fbc93562942c10f631c7f415f8fdba2e (patch) | |
| tree | e6126408287223cec556ff7ed7b8c026c81bb958 /techlibs/xilinx/cells_sim.v | |
| parent | e0bdf5d7a9280c9f975a34fc265793de86fd9bec (diff) | |
| download | yosys-21ce1b37fbc93562942c10f631c7f415f8fdba2e.tar.gz yosys-21ce1b37fbc93562942c10f631c7f415f8fdba2e.tar.bz2 yosys-21ce1b37fbc93562942c10f631c7f415f8fdba2e.zip | |
abc9_ops: -check for negative arrival/required times
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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