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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-03 14:57:17 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-03 14:57:17 +0100 |
| commit | 34d2fbd2f96a8789aa7eb655318308e11949eb7a (patch) | |
| tree | 246fac88cc076f041cb9194bf6e4f954d50fd78c /techlibs/xilinx/cells_sim.v | |
| parent | 7033503cd9e40e16c11fe6c805a436b0e23989dd (diff) | |
| download | yosys-34d2fbd2f96a8789aa7eb655318308e11949eb7a.tar.gz yosys-34d2fbd2f96a8789aa7eb655318308e11949eb7a.tar.bz2 yosys-34d2fbd2f96a8789aa7eb655318308e11949eb7a.zip | |
Add opt_lut_ins pass. (#1673)
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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