aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/cells_sim.v
diff options
context:
space:
mode:
authorEddie Hung <eddieh@ece.ubc.ca>2019-04-04 07:54:42 -0700
committerEddie Hung <eddieh@ece.ubc.ca>2019-04-04 07:54:42 -0700
commit572603409c3f5524f8d4d9e43a168bcfccd94465 (patch)
tree042e21e109701a41623170c04ee3c1467a681fc9 /techlibs/xilinx/cells_sim.v
parent77755b5a662a11a3dcc18c070e6ea859104fc872 (diff)
parentd9cb787391143a1749954f9e442fd37a13668b08 (diff)
downloadyosys-572603409c3f5524f8d4d9e43a168bcfccd94465.tar.gz
yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.tar.bz2
yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.zip
Merge branch 'map_cells_before_map_luts' into xc7srl
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions