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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 15:00:16 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-06 15:00:16 -0800 |
| commit | 66698cb6fd0e33a27197b7412e094dc77363b5e5 (patch) | |
| tree | 8f20d4996477aec3eacc8695aa50ab57703e0b04 /techlibs/xilinx/cells_sim.v | |
| parent | 898a8fa7acfd0b78ce848af6bf893fe5fc489b52 (diff) | |
| parent | 28bf712372c494043c7adc0de904925a9199c939 (diff) | |
| download | yosys-66698cb6fd0e33a27197b7412e094dc77363b5e5.tar.gz yosys-66698cb6fd0e33a27197b7412e094dc77363b5e5.tar.bz2 yosys-66698cb6fd0e33a27197b7412e094dc77363b5e5.zip | |
Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor
Refactor abc9's DSP48E1 handling
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index c27b0f02b..1cd4d2f30 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2160,9 +2160,15 @@ module DSP48E1 ( output reg [3:0] CARRYOUT, output reg MULTSIGNOUT, output OVERFLOW, +`ifdef YOSYS + (* abc9_arrival = \DSP48E1.P_arrival () *) +`endif output reg signed [47:0] P, output reg PATTERNBDETECT, output reg PATTERNDETECT, +`ifdef YOSYS + (* abc9_arrival = \DSP48E1.PCOUT_arrival () *) +`endif output [47:0] PCOUT, output UNDERFLOW, input signed [29:0] A, @@ -2235,6 +2241,77 @@ module DSP48E1 ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +`ifdef YOSYS + function integer \DSP48E1.P_arrival ; + begin + \DSP48E1.P_arrival = 0; + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.P_arrival = 329; + // Worst-case from CREG and MREG + else if (CREG != 0) \DSP48E1.P_arrival = 1687; + else if (MREG != 0) \DSP48E1.P_arrival = 1671; + // Worst-case from AREG and BREG + else if (AREG != 0) \DSP48E1.P_arrival = 2952; + else if (BREG != 0) \DSP48E1.P_arrival = 2813; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (PREG != 0) \DSP48E1.P_arrival = 329; + // Worst-case from CREG and MREG + else if (CREG != 0) \DSP48E1.P_arrival = 1687; + else if (MREG != 0) \DSP48E1.P_arrival = 1671; + // Worst-case from AREG, ADREG, BREG, DREG + else if (AREG != 0) \DSP48E1.P_arrival = 3935; + else if (DREG != 0) \DSP48E1.P_arrival = 3908; + else if (ADREG != 0) \DSP48E1.P_arrival = 2958; + else if (BREG != 0) \DSP48E1.P_arrival = 2813; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.P_arrival = 329; + // Worst-case from AREG, BREG, CREG + else if (CREG != 0) \DSP48E1.P_arrival = 1687; + else if (AREG != 0) \DSP48E1.P_arrival = 1632; + else if (BREG != 0) \DSP48E1.P_arrival = 1616; + end + //else + // $error("Invalid DSP48E1 configuration"); + end + endfunction + function integer \DSP48E1.PCOUT_arrival ; + begin + \DSP48E1.PCOUT_arrival = 0; + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; + // Worst-case from CREG and MREG + else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; + else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; + // Worst-case from AREG and BREG + else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098; + else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; + // Worst-case from CREG and MREG + else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; + else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; + // Worst-case from AREG, ADREG, BREG, DREG + else if (AREG != 0) \DSP48E1.PCOUT_arrival = 4083; + else if (DREG != 0) \DSP48E1.PCOUT_arrival = 4056; + else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; + else if (ADREG != 0) \DSP48E1.PCOUT_arrival = 2859; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; + // Worst-case from AREG, BREG, CREG + else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; + else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780; + else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765; + end + //else + // $error("Invalid DSP48E1 configuration"); + end + endfunction +`endif + initial begin `ifndef YOSYS if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); |