aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/cells_sim.v
diff options
context:
space:
mode:
authorEddie Hung <eddie@fpgeh.com>2019-06-21 15:45:51 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-21 15:45:51 -0700
commit6a0fb3035ebe7d096a22b13a2fb90de891d6ffe5 (patch)
treeb406d11f5c62160fab33198ab9dd55e31bfb105e /techlibs/xilinx/cells_sim.v
parent3cf2afc2802e32288b2f83da6ebe4b4fbfa8e013 (diff)
downloadyosys-6a0fb3035ebe7d096a22b13a2fb90de891d6ffe5.tar.gz
yosys-6a0fb3035ebe7d096a22b13a2fb90de891d6ffe5.tar.bz2
yosys-6a0fb3035ebe7d096a22b13a2fb90de891d6ffe5.zip
Replace assert with error message
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions