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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 09:17:53 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 7d86aceee326d214b9e31602f00f6196d1213c9e (patch) | |
| tree | c7300ba6fb96f7a1e4a2c038c4bc4a2355b26933 /techlibs/xilinx/cells_sim.v | |
| parent | 3728ef1765b3b3375481222832d3a17600ae0312 (diff) | |
| download | yosys-7d86aceee326d214b9e31602f00f6196d1213c9e.tar.gz yosys-7d86aceee326d214b9e31602f00f6196d1213c9e.tar.bz2 yosys-7d86aceee326d214b9e31602f00f6196d1213c9e.zip | |
Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5dadf1ef3..4873a66f3 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1421,11 +1421,11 @@ module RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792 $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); $setup(A4, posedge WCLK &&& IS_WCLK_INVERTED && WE, 66); -`ifndef __ICARUS__ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153; -`endif + if (!IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153; + if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153; + if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153; + if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153; // Captured by $__ABC9_RAM6 //({A0,DPRA0} => {SPO,DPO}) = 642; //({A1,DPRA1} => {SPO,DPO}) = 631; @@ -1473,10 +1473,9 @@ module RAM32X1D_1 ( $setup(A3, negedge WCLK &&& WE, 68); // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792 $setup(A4, negedge WCLK &&& WE, 66); -`ifndef __ICARUS__ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153; -`endif + if (WE) (negedge WCLK => (SPO : D)) = 1153; + if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; // Captured by $__ABC9_RAM6 //({A0,DPRA0} => {SPO,DPO}) = 642; //({A1,DPRA1} => {SPO,DPO}) = 631; @@ -1530,11 +1529,11 @@ module RAM64X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818 $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66); $setup(A5, negedge WCLK &&& IS_WCLK_INVERTED && WE, 66); -`ifndef __ICARUS__ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153; - if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153; -`endif + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153; + if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D)) = 1153; + if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153; // Captured by $__ABC9_RAM6 //({A0,DPRA0} => {SPO,DPO}) = 642; //({A1,DPRA1} => {SPO,DPO}) = 631; @@ -1581,10 +1580,9 @@ module RAM64X1D_1 ( $setup(A4, negedge WCLK &&& WE, 68); // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818 $setup(A5, negedge WCLK &&& WE, 66); -`ifndef __ICARUS__ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 - if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153; -`endif + if (WE) (negedge WCLK => (SPO : D)) = 1153; + if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; endspecify endmodule |