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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:21 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:21 -0800 |
| commit | a73f96594f4688afc85098b485ef7788e79f5c33 (patch) | |
| tree | 8b4fdf160bcb8a8db62a309fd409096a721bb3c7 /techlibs/xilinx/cells_sim.v | |
| parent | 9935370ada858da56b5d61a3806768af11565a47 (diff) | |
| parent | 5d009964266e3b52a01c72ee930601d0ebf3a838 (diff) | |
| download | yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.gz yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.bz2 yosys-a73f96594f4688afc85098b485ef7788e79f5c33.zip | |
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3ed0759db..f9ce496ff 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1185,10 +1185,10 @@ module RAM64M ( output DOB, output DOC, output DOD, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, input DIA, input DIB, input DIC, @@ -1230,14 +1230,14 @@ module RAM64M8 ( output DOF, output DOG, output DOH, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, - input [4:0] ADDRE, - input [4:0] ADDRF, - input [4:0] ADDRG, - input [4:0] ADDRH, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, + input [5:0] ADDRE, + input [5:0] ADDRF, + input [5:0] ADDRG, + input [5:0] ADDRH, input DIA, input DIB, input DIC, |