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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 13:36:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 13:36:27 -0700 |
| commit | a9a140aa6c84e71edc1a244cfe363400c7e09d90 (patch) | |
| tree | 7c6a9c571fc2c3c142bd936aca165061c31e7585 /techlibs/xilinx/cells_sim.v | |
| parent | 603fe9cda9ea6c18374ae4c5545d55b97cfa4c81 (diff) | |
| download | yosys-a9a140aa6c84e71edc1a244cfe363400c7e09d90.tar.gz yosys-a9a140aa6c84e71edc1a244cfe363400c7e09d90.tar.bz2 yosys-a9a140aa6c84e71edc1a244cfe363400c7e09d90.zip | |
Fix broken MUXFx box, use MUXF7x2 box instead
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3937d3536..d1877cf1a 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -171,9 +171,9 @@ endmodule `ifdef _ABC (* abc_box_id = 3, lib_whitebox *) -module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); - assign O = S1 ? (S0 ? I3 : I2) - : (S0 ? I1 : I0); +module \$__XILINX_MUXF7x2 (output O0, O1, input I0, I1, I2, I3, S); + assign O0 = S ? I1 : I0; + assign O1 = S ? I3 : I2; endmodule `endif |