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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 08:58:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 08:58:57 -0700 |
| commit | ae89e6ab26d2d87a604e20ebc14dcda8c9901585 (patch) | |
| tree | a8b9fb4f00eef4abaa1c476e488ded535f372dc6 /techlibs/xilinx/cells_sim.v | |
| parent | 4f44e3399ba6c959c830943c44c4ad728be895fa (diff) | |
| download | yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.tar.gz yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.tar.bz2 yosys-ae89e6ab26d2d87a604e20ebc14dcda8c9901585.zip | |
Add whitebox support to DRAM
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 9db52b67a..29c79f689 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,8 +281,9 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +(* abc_box_id = 4, lib_whitebox *) module RAM64X1D ( - (* abc_flop_q *) output DPO, SPO, + output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 @@ -294,12 +295,15 @@ module RAM64X1D ( reg [63:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; +`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[a] <= D; +`endif endmodule +(* abc_box_id = 5, lib_whitebox *) module RAM128X1D ( - (* abc_flop_q *) output DPO, SPO, + output DPO, SPO, input D, WCLK, WE, input [6:0] A, DPRA ); @@ -308,8 +312,10 @@ module RAM128X1D ( reg [127:0] mem = INIT; assign SPO = mem[A]; assign DPO = mem[DPRA]; +`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[A] <= D; +`endif endmodule module SRL16E ( |