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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:00:03 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:00:03 -0700 |
| commit | b33ecd2a746b734fda33d8535afecf76bd35f59c (patch) | |
| tree | 42787f772fb84797029653456f652a395225f19f /techlibs/xilinx/cells_sim.v | |
| parent | cea7441d8ae7df8d22f510e6a101ec46a9d7751e (diff) | |
| download | yosys-b33ecd2a746b734fda33d8535afecf76bd35f59c.tar.gz yosys-b33ecd2a746b734fda33d8535afecf76bd35f59c.tar.bz2 yosys-b33ecd2a746b734fda33d8535afecf76bd35f59c.zip | |
Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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