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| author | David Shah <dave@ds0.me> | 2019-08-08 11:18:37 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:18:37 +0100 |
| commit | d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5 (patch) | |
| tree | de262053843adbc7b4c3b520609eccc2b385e762 /techlibs/xilinx/cells_sim.v | |
| parent | e7dbe7bb3de256f0ea89eb07647799b1e8d65bbe (diff) | |
| download | yosys-d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5.tar.gz yosys-d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5.tar.bz2 yosys-d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5.zip | |
DSP48E1 sim model: fix seq tests and add preadder tests
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions