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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:16:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:16:50 -0700 |
| commit | efd04880dbeb2021c503c82ad962fe8c5d6802d4 (patch) | |
| tree | 0d2f1d1c8c211d24b2d3f1878b7c70f4bd98997f /techlibs/xilinx/cells_sim.v | |
| parent | fb8fab4a29e5a3978cadf2b1bd8920b772150028 (diff) | |
| download | yosys-efd04880dbeb2021c503c82ad962fe8c5d6802d4.tar.gz yosys-efd04880dbeb2021c503c82ad962fe8c5d6802d4.tar.bz2 yosys-efd04880dbeb2021c503c82ad962fe8c5d6802d4.zip | |
Add RAM32X1D support
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3a4540b83..50d588a9e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -278,6 +278,23 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +module RAM32X1D ( + output DPO, SPO, + input D, WCLK, WE, + input A0, A1, A2, A3, A4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, +); + parameter INIT = 32'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [31:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, |